Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Theoretical Computer Science
Patterns in property specifications for finite-state verification
Proceedings of the 21st international conference on Software engineering
PROPEL: an approach supporting property elucidation
Proceedings of the 24th International Conference on Software Engineering
Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking
Synchronous Observers and the Verification of Reactive Systems
AMAST '93 Proceedings of the Third International Conference on Methodology and Software Technology: Algebraic Methodology and Software Technology
IF-2.0: A Validation Environment for Component-Based Real-Time Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CADP - A Protocol Validation and Verification Toolbox
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Real-time specification patterns
Proceedings of the 27th international conference on Software engineering
Time Petri Nets Analysis with TINA
QEST '06 Proceedings of the 3rd international conference on the Quantitative Evaluation of Systems
Using context descriptions and property definition patterns for software formal verification
ICSTW '08 Proceedings of the 2008 IEEE International Conference on Software Testing Verification and Validation Workshop
Specifying precise use cases with use case charts
MoDELS'05 Proceedings of the 2005 international conference on Satellite Events at the MoDELS
Trust in MDE components: the DOMINO experiment
Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems
Application of partial-order methods for the verification of closed-loop SDL systems
Proceedings of the 2011 ACM Symposium on Applied Computing
Improving formal verification practicability through user oriented models and context-awareness
Proceedings of the 8th International Workshop on Model-Driven Engineering, Verification and Validation
Use cases for context aware model-checking
MODELS'11 Proceedings of the 2011th international conference on Models in Software Engineering
Model checking of OSEK/VDX OS design model based on environment modeling
ICTAC'12 Proceedings of the 9th international conference on Theoretical Aspects of Computing
Automated measurement of models of requirements
Software Quality Control
Improving model checking with context modelling
Advances in Software Engineering
| Hi-index | 0.00 |
A well known challenge in the formal methods domain is to improve their integration with practical engineering methods. In the context of embedded systems, model checking requires first to model the system to be validated, then to formalize the properties to be satisfied, and finally to describe the behavior of the environment. This last point which we name as the proof context is often neglected. It could, however, be of great importance in order to reduce the complexity of the proof. The question is then how to formalize such a proof context. We experiment a language, named CDL (Context Description Language), for describing a system environment using actors and sequence diagrams, together with the properties to be checked. The properties are specified with textual patterns and attached to specific regions in the context. Our contribution is a report on several industrial embedded system applications.