Verifying clock schedules

Clock Skew Optimization for Peak Current Reduction

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimization of synchronous circuits

Logic Synthesis and Verification

On the performance of level-clocked circuits

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Slack borrowing in flip-flop based sequential circuits

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Binning optimization based on SSTA for transparently-latched circuits

Proceedings of the 2009 International Conference on Computer-Aided Design

Multi-level clustering for clock skew optimization

Proceedings of the 2009 International Conference on Computer-Aided Design

Statistical timing verification for transparently latched circuits through structural graph traversal

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods

Proceedings of the International Conference on Computer-Aided Design