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Transactional memory: architectural support for lock-free data structures
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Thin locks: featherweight synchronization for Java
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
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Safe memory reclamation for dynamic lock-free objects using atomic reads and writes
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A Practical Multi-word Compare-and-Swap Operation
DISC '02 Proceedings of the 16th International Conference on Distributed Computing
Nonblocking k-compare-single-swap
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Using cache memory to reduce processor-memory traffic
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ICDCS '03 Proceedings of the 23rd International Conference on Distributed Computing Systems
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Language support for lightweight transactions
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
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JVM'01 Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1
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We introduce Transient Blocking Synchronization (TBS), a new approach to hardware synchronization for mega-scale distributed-memory multiprocessor machines. Such machines, with thousands of processors and controller based memory modules, are essentially distributed networks, and one must search for new paradigms that provide hardware synchronization support with high levels of robustness and minimal protocol and communication overhead. It is our claim that the semantics of non-blocking synchronization primitives such as Compare &Swap and LoadLinked/StoreConditional on the one hand, and blocking ones such as Full/Empty-bits on the other, will introduce high communication and space costs when implemented on large scale machines. TBS is a novel hardware synchronization paradigm resting between the classic blocking and non-blocking approaches to synchronization. It is an example of how, based on very weak "transient" hardware blocking, that is, blocking that may be revoked at any time, one can provide non-blocking universal synchronization with low communication and space complexity. This paper presents a set of simple TBS single-location synchronization operations and shows that they provide low cost non-blocking emulations of all known read-modify-write operations. Moreover, it shows that the combination of TBS with hardware supported transactional bits, a variation on traditional hardware full/empty bits, can provide low message cost implementations of multi-word transactional operations.