A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

Authors:
L. Siéler;C. Tanougast;A. Bouridane
Affiliations:
Université Blaise Pascal, LASMEA, Clermond-Ferrand, France;Université Paul Verlaine, LICM-ISEA, Metz, France;Northumbria University at Newcastle, Newcastle upon Tyne NE2 1XE, UK
Venue:
Microprocessors & Microsystems
Year:
2010

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Abstract

This paper presents a novel and optimized embedded architecture based FPGA for an efficient and fast computation of grey level co-occurrence matrices (GLCM) and Haralick textures features for use in high throughput image analysis applications where time performance is critical. The originality of this architecture allows for a scalable and a totally embedded on Chip FPGA for the processing of large images. The architecture was implemented on Xilinx Virtex-FPGAs without the use of external memory and/or host machine. The implementations demonstrate that our proposed architecture can deliver a high reduction of the memory and FPGA logic requirements when compared with the state of the art counterparts and it also achieves much improved processing times when compared against optimized software implementation running on a conventional general purpose processor.