A4.2 mW 5.7-GHz frequency synthesizer with dynamic-logic (TSPC) frequency divider

  • Authors:

  • J. P. Carmo;P. M. Mendes;J. H. Correia

  • Affiliations:

  • University of Minho, Dept. Industrial Electronics, Guimaraes, Portugal;University of Minho, Dept. Industrial Electronics, Guimaraes, Portugal;University of Minho, Dept. Industrial Electronics, Guimaraes, Portugal

  • Venue:
  • ICT'09 Proceedings of the 16th international conference on Telecommunications
  • Year:
  • 2009

Quantified Score

Hi-index 0.01

Visualization

Abstract

This paper presents a Phase-Locked Loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in tbe UMC RF 0.18 µm CMOS process. Tbe PLL produces a set of different 16 digitally programmable frequencies in tbe [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback path. Simulations shown a total power consumption of 4.2 mW. Target applications are wireless sensors and microsystems applications that need RF transceivers for operation in the 5.7 GHz band.