A design for passive RFID system on a chip

  • Authors:

  • Chan-won Park;Gil-young Choi;Jong-suk Chae;Bo-gwan Kim

  • Affiliations:

  • Electronics and Telecommunications Research Institute;Electronics and Telecommunications Research Institute;Electronics and Telecommunications Research Institute;Chungnam National University

  • Venue:
  • ICACT'09 Proceedings of the 11th international conference on Advanced Communication Technology - Volume 1
  • Year:
  • 2009

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Abstract

The spread of RFID application need IC-based solution to reduce the size and cost of reader. The design result and architecture of UHF band passive RFID reader system on a chip is presented in this paper. The chip includes processor core, Flash memory, RFID digital baseband, DAC/ADC, RF based on direct-conversion architecture, user interface block. RFID protocol meets the EPC Class-1 Generation 2 and ISO-18000-6C standards. The chip can cover all passive RFID frequency range from 860MHz to 960MHz and provide low power consumption as 78mA from 1.8V when output power is+5dBm. The package is 8mm × 8mm CABGA made with 4mm × 4mm die area.