Circuit implementation of SVM training

Authors:
Sergio Decherchi;Paolo Gastaldo;Mauro Parodi;Rodolfo Zunino
Affiliations:
Department of Biophysical and Electronic Engineering, University of Genoa, Italy;Department of Biophysical and Electronic Engineering, University of Genoa, Italy;Department of Biophysical and Electronic Engineering, University of Genoa, Italy;Department of Biophysical and Electronic Engineering, University of Genoa, Italy
Venue:
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Year:
2009

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Abstract

A central issue in computational intelligence is the training phase of a learning machine. In classification problems, in particular, Support Vector Machines are one of the most effective tools. In this work an analog low-complexity circuital implementation is proposed to address the learning stage of SVMs. The circuit is a co-content minimization network based on a suitable SVM formulation embedding bias removal. Moreover the circuit complexity (i.e. the density of the kernel matrix) is effectively controlled by resorting to a proper kernel function. Experimental evidence shows the effectiveness of the proposed approach.