Embedding graphs in books: a layout problem with applications to VLSI design
SIAM Journal on Algebraic and Discrete Methods
Group action graphs and parallel architectures
SIAM Journal on Computing
Trivalent Cayley graphs for interconnection networks
Information Processing Letters
Shortest routing in trivalent Cayley graph network
Information Processing Letters
Hamilton cycles in trivalent Cayley graphs
Information Processing Letters
Embedding de Bruijn, Kautz and shuffle-exchange networks in books
Discrete Applied Mathematics
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Book embedding of graphs is one of the graph layout problem. It is useful for the multiprocessor network layout or the fault-tolerant processor arrays. We show that the trivalent Cayley graphs proposed by Vadapalli and Srimani can be embedded in five pages, and show some additional results on cube-connected cycles.