Validation Coverage for a Component-based SDL model of a Railway Signaling System

Authors:
M. Banci;M. Becucci;A. Fantechi;E. Spinicci
Affiliations:
Dipartimento di Sistemi e Informatica, Università degli Studi di Firenze, Firenze, Italy;Dipartimento di Sistemi e Informatica, Università degli Studi di Firenze, Firenze, Italy;Dipartimento di Sistemi e Informatica, Università degli Studi di Firenze, Firenze, Italy;Dipartimento di Sistemi e Informatica, Università degli Studi di Firenze, Firenze, Italy
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2005

Citing 3
Cited 1

Statecharts: A visual formalism for complex systems

Science of Computer Programming
Design and validation of computer protocols

Design and validation of computer protocols
Validating SDL Specifications: an Experiment

Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX

A story about formal methods adoption by a railway signaling manufacturer

FM'06 Proceedings of the 14th international conference on Formal Methods

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present an application of formal verification techniques to a component-based SDL model of a railway signalling system lent by General Electric Transportation Systems. A MSC-driven validation technique has been applied to verify the multiple-configuration features of the system. This work addresses the problem of validating a component-oriented designed SDL model, with a partial reuse of previously verified MSC scenarios if a new component is introducing or modified: some possible solutions based on the coverage metrics and information provided by the adopted tools are discussed.