Analog VLSI and neural systems
Analog VLSI and neural systems
Distinctive Image Features from Scale-Invariant Keypoints
International Journal of Computer Vision
Discriminative techniques for the recognition of complex-shaped objects
Discriminative techniques for the recognition of complex-shaped objects
Optimizing Compiler for the CELL Processor
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
How Close Are We to Understanding V1?
Neural Computation
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Derivation and Analysis of Basic Computational Operations of Thalamocortical Circuits
Journal of Cognitive Neuroscience
Engines of the brain: the computational instruction set of human cognition
AI Magazine - Special issue on achieving human-level AI through integrated systems and research
From synapse to psychology: emergence of a language, speech, and vision engine from bottom-up brain modeling
Robust Object Recognition with Cortex-Like Mechanisms
IEEE Transactions on Pattern Analysis and Machine Intelligence
Beautiful Code: Leading Programmers Explain How They Think (Theory in Practice (O'Reilly))
Beautiful Code: Leading Programmers Explain How They Think (Theory in Practice (O'Reilly))
Accelerating Brain Circuit Simulations of Object Recognition with CELL Processors
IWIA '07 Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
Patterns for parallel programming
Patterns for parallel programming
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
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Even though computing systems have increased the number of transistors, the switching speed, and the number of processors, most programs exhibit limited speedup due to the serial dependencies of existing algorithms. Analysis of intrinsically parallel systems such as brain circuitry have led to the identification of novel architecture designs, and also new algorithms than can exploit the features of modern multiprocessor systems. In this article we describe the details of a brain derived vision (BDV) algorithm that is derived from the anatomical structure, and physiological operating principles of thalamo-cortical brain circuits. We show that many characteristics of the BDV algorithm lend themselves to implementation on IBM CELL architecture, and yield impressive speedups that equal or exceed the performance of specialized solutions such as FPGAs. Mapping this algorithm to the IBM CELL is non-trivial, and we suggest various approaches to deal with parallelism, task granularity, communication, and memory locality. We also show that a cluster of three PS3s (or more) containing IBM CELL processors provides a promising platform for brain derived algorithms, exhibiting speedup of more than 140× over a desktop PC implementation, and thus enabling real-time object recognition for robotic systems.