Analyzing LTL Model Checking Techniques for Plan Synthesis and Controller Synthesis (Work in Progress)

Authors:
Sylvain Kerjean;Froduald Kabanza;Richard St-Denis;Sylvie Thiébaux
Affiliations:
Département d'informatique, Université de Sherbrooke, Sherbrooke (Québec), Canada J1K 2R1;Département d'informatique, Université de Sherbrooke, Sherbrooke (Québec), Canada J1K 2R1;Département d'informatique, Université de Sherbrooke, Sherbrooke (Québec), Canada J1K 2R1;National ICT Australia and Computer Science Laboratory, The Australian National University, Canberra ACT 0200 Australia
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2006

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Abstract

In this paper, we present alternative means of handling invariances in reachability testing, either by formula progression or compilation into Buchi automata. These alternatives are presented in connection with three different applications of model checking: verification, plan synthesis as well as heuristic guidance of AI planning, and controller synthesis. We include results from benchmarks obtained from preparatory experiments with model checking using a family of LTL2Buchi translators and formula progression.