Slicing-based Hardware/Software Co-design Methodology From Functional Specifications

  • Authors:

  • Shunsuke Sasaki;Tasuku Nishihara;Masahiro Fujita

  • Affiliations:

  • Department of Electronics Engineering, Graduate School of Engineering, The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, Tokyo, Japan;Department of Electronics Engineering, Graduate School of Engineering, The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, Tokyo, Japan;VLSI Design and Education Center, The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, Tokyo, Japan

  • Venue:
  • Electronic Notes in Theoretical Computer Science (ENTCS)
  • Year:
  • 2006

Quantified Score

Hi-index 0.00

Visualization

Abstract

Program slicing is a software analysis technique and generates System Dependence Graphs (SDGs) by which dependences among program statements can be identified. In this paper, we propose a new hardware-software co-design methodology based on the static and partially dynamic dependence analysis with SDG. We start with any combinations of C, C++, and SpecC descriptions so that flexible functional specifications of the HW/SW systems can be made. First of all, the input descriptions are analyzed and verified with the SDG generated from the input descriptions. Actual analyses and verifications are based on static ones but partially with dynamic ones as well, and fairly large descriptions can be processed. After these analyses, we divide the system into hardware and software parts by optimizing the design descriptions and introducing parallelism if necessary. In this HW/SW partitioning, SDG generated from C / C++ / SpecC design descriptions is fully utilized to extract / convert / pack the HW parts from the entire descriptions. This flexibility of HW/SW partitioning is one of the main differences from previous HW/SW partitioning methods. The extracted HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. As the last step, the generated RTL descriptions together with SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designer-specified properties may be model checked with these final design descriptions. These equivalence checking and model checking can be realized by first translating the HW/SW design descriptions into FSM type representations. The translated FSM type representations are further processed by existing formal verifiers. We present the proposed HW/SW co-design methodology with an illustrating example as well as actual application to real designs and demonstrate the usefulness of our approach.