Design and validation of computer protocols
Design and validation of computer protocols
A framework for verifying discrete event models within a DEVS-based system development methodology
Transactions of the Society for Computer Simulation International
Discrete event modelng and simulation technologies
Communication and Concurrency
Theory of Modeling and Simulation
Theory of Modeling and Simulation
A Real-Time Discrete Event System Specification Formalismfor Seamless Real-Time Software Development
Discrete Event Dynamic Systems
Real time simulation framework for RT-DEVS models
Transactions of the Society for Computer Simulation International - Recent advances in DEVS methodology--part II
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
From domain specific languages to DEVS components: application to cognitive M&S
Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium
Modeling portlet aggregation through statecharts
WISE'06 Proceedings of the 7th international conference on Web Information Systems
DEVSML 2.0: the language and the stack
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
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Discrete EVent Systems Specification (DEVS) formalism supports specification of discrete event models in a hierarchical modular manner. This paper proposes a DEVS modeling language called DEVS Specification Language (DEVSpecL) based on which discrete event systems are modeled, simulated and analyzed within a DEVS-based framework for seamless systems design. Models specified in DEVSpecL can be translated in different forms of codes by code generators, which are executed with various tools for models verification, logical analysis, performance evaluation, and others.