Modeling architectures for VLSI implementations of fuzzy logic systems

  • Authors:

  • B. Roche;T. M. McGinnity;L. P. Maguire;L. J. McDaid

  • Affiliations:

  • -;-;-;-

  • Venue:
  • Information Sciences: an International Journal
  • Year:
  • 1999

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Abstract

A model for predicting silicon area occupied by a fuzzy logic system implemented in VLSI is presented. The model aims to allow designers to estimate the feasibility of implementing their fuzzy logic system in hardware and should also enable the identification of core-limited or interconnect-limited designs. A set of examples showing typical results are presented. These illustrate the dominant impact of interconnect on silicon area in hardware implementations of fuzzy logic systems.