Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Architecture of the Symbolics 3600
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
An efficient LISP-execution architecture with a new representation for list structures
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Compact Encodings of List Structure
ACM Transactions on Programming Languages and Systems (TOPLAS)
Managing Reentrant Structures Using Reference Counts
ACM Transactions on Programming Languages and Systems (TOPLAS)
An empirical study of list structure in Lisp
Communications of the ACM
List processing in real time on a serial computer
Communications of the ACM
Compact list representation: definition, garbage collection, and system implementation
Communications of the ACM
A method for overlapping and erasure of lists
Communications of the ACM
A performance evaluation of a Lisp-based data-driven machine (EM-3)
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Implementation of multilisp: Lisp on a multiprocessor
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
LFP '82 Proceedings of the 1982 ACM symposium on LISP and functional programming
A multiprocessing system for the direct execution of LISP
CAW '78 Proceedings of the fourth workshop on Computer architecture for non-numeric processing
Experience with a microprogrammed Interlisp system
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Characterization of VAX Macsyma
SYMSAC '81 Proceedings of the fourth ACM symposium on Symbolic and algebraic computation
| Hi-index | 0.00 |
In this paper, we present a Lisp machine architecture that supports efficient list manipulation. This Lisp architecture is organized as two processing units: a List Processor (LP), that performs all list related operations and manages the list memory, and an Evaluation Processor (EP), that maintains the addressing and control environment. The LP contains a translation table (LPT) that maps a small set of list identifiers into the physical memory addresses of objects. Essentially, the LP and LPT virtualize a list. The EP then operates on these virtualized lists. Such an organization permits the overlap of EP function evaluation with LP memory accesses and management, thus reducing the performance penalties typically associated with Lisp list manipulation activities. We used trace-driven simulations to evaluate this architecture. From our evaluation a relatively small LPT is seen to be sufficient, and to yield “hit rates” on data accesses higher than those of a data cache of comparable size.