A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
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This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise-ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-VP-P input signal swing. The occupied silicon area is 0.5-mm2; and the power consumption of 94-mW from a 1.2-V supply.