A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2

Authors:
Shan Gao;Taku Kihara;Sho Shimizu;Yutaka Arakawa;Naoaki Yamanaka;Akifumi Watanabe
Affiliations:
Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Kohoku-ku, Yokohama, Japan;Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Kohoku-ku, Yokohama, Japan;Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Kohoku-ku, Yokohama, Japan;Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Kohoku-ku, Yokohama, Japan;Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Kohoku-ku, Yokohama, Japan;IPFlex Inc., Shinagawa-ku, Tokyo, Japan
Venue:
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Year:
2009

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Abstract

This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the on-chip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.