Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Regular and irregular progressive edge-growth tanner graphs
IEEE Transactions on Information Theory
Algebraic construction of sparse matrices with large girth
IEEE Transactions on Information Theory
Asymptotic Spectra of Trapping Sets in Regular and Irregular LDPC Code Ensembles
IEEE Transactions on Information Theory
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A lot of works concerning LDPC codes construction has been published so far. However, it is well known that efficient partially parallel hardware decoder architectures are allowed only for LDPC codes with blockwise partitioned structure of the parity check matrix, called structured LDPC codes. Two main steps in the structured LDPC code parity check matrix construction are the seed matrix (seed graph) construction and expansion of the seed matrix (seed graph). In this paper we present a flexible method for seed matrix expansion by computer search technique for the optimum shift values of the circulant submatrices. The proposed algorithm aims at reducing existence in the code graph of small cycles with low external connectivity that constitute structures known as Stopping Sets and Trapping Sets that are harmful to the code performance, especially in the high SNR region. The algorithm can be used for regular or irregular code construction of any block length and code rate.