On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems

  • Authors:

  • Felix Gutierrez;Shatam Agarwal;Kristen Parrish;Theodore S. Rappaport

  • Affiliations:

  • Wireless Networking and Communications Group, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Wireless Networking and Communications Group, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Wireless Networking and Communications Group, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Wireless Networking and Communications Group, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX

  • Venue:
  • IEEE Journal on Selected Areas in Communications - Special issue on realizing GBPS wireless personal area networks
  • Year:
  • 2009

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Abstract

This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for wireless personal area networks (WPANs) promise to reduce interconnection losses and greatly reduce wireless transceiver costs, while providing unprecedented flexibility for device manufacturers. This paper presents the current state of research in on-chip integrated antennas, highlights several pitfalls and challenges for on-chip design, modeling, and measurement, and proposes several antenna structures that derive from the microwave microstrip and amateur radio art. This paper also describes an experimental test apparatus for performing measurements on RFIC systems with on-chip antennas developed at The University of Texas at Austin.