Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
A Gaussian Noise Generator for Hardware-Based Simulations
IEEE Transactions on Computers
Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes
IEEE Transactions on Information Theory
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
Codes on graphs: normal realizations
IEEE Transactions on Information Theory
Finite-length analysis of low-density parity-check codes on the binary erasure channel
IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices
IEEE Transactions on Information Theory
Asymptotic Spectra of Trapping Sets in Regular and Irregular LDPC Code Ensembles
IEEE Transactions on Information Theory
Iterative decoder architectures
IEEE Communications Magazine
A relaxed half-stochastic iterative decoder for LDPC codes
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes
IEEE Transactions on Information Theory
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Journal of Electrical and Computer Engineering - Special issue on iterative signal processing in communications
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders strongly affect which absorbing sets dominate in the error-floor region. We show that conventional sum-product decoder implementations of the (2209, 1978) array-based LDPC code allow low-weight absorbing sets to have a strong effect, and, as a result, elevate the error floor. Dually-quantized sum-product decoders and approximate sum-product decoders alleviate the effects of low-weight absorbing sets, thereby lowering the error floor.