Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
Space Time Coding for Broadband Wireless Communications
Space Time Coding for Broadband Wireless Communications
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
Diversity and multiplexing: a fundamental tradeoff in multiple-antenna channels
IEEE Transactions on Information Theory
On maximum-likelihood detection and the search for the closest lattice point
IEEE Transactions on Information Theory
From theory to practice: an overview of MIMO space-time coded wireless systems
IEEE Journal on Selected Areas in Communications
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Iterative QR decomposition architecture using the modified gram-schmidt algorithm for MIMO systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
A radius adaptive K-Best decoder with early termination: algorithm and VLSI architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
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This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequency subcarriers for orthogonal frequency-division multiplexing (OFDM) based systems. A 20 times area reduction is achieved, even without interleaving of subcarriers compared to the direct-mapped architecture. The sphere decoder supports multiple configurations: antenna arrays from 2×2 to 16×16, constellation sizes from binary phase-shift keying (BPSK) to 64-QAM (quadrature-amplitude modulation), and 16-128 subcarriers. The peak estimated data rate exceeds 1.5 Gbits/s of ideal throughput in a 16-MHz bandwidth. The core area is estimated at 0.31 mm2 in a standard 90-nm CMOS technology. The estimated power consumption is 33 mW in the 16×16 64-QAM mode at 256 MHz from a 1-V supply voltage.