A 60-GHz phased array receiver front-end in 0.13-µm CMOS technology

Authors:
Chao-Shiun Wang;Juin-Wei Huang;Kun-Da Chu;Chorng-Kuang Wang
Affiliations:
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Novatek Microelectronics Corp., Hsinchu, Taiwan and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;MStar Semiconductor, Inc, Hsinchu, Taiwan and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, ROC;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

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Abstract

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, a gm-boosted current-reuse low-noise amplifier (LNA), a subharmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The gm-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate downconversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-µm 1P8M RF CMOS technology, the chip occupies an active area of 1.1 × 1.2 mm2. The measured conversion gain and input P1 dB of the single receiver path are 30 dB and --27 dBm, respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.