Versatile design of shared vector coprocessors for multicores
Microprocessors & Microsystems
Importance of single-core performance in the multicore era
ACSC '12 Proceedings of the Thirty-fifth Australasian Computer Science Conference - Volume 122
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Applications of different categories contain varying levels of data, instruction and thread-level parallelism inherently. It's important to explore the potential coarse-grain thread-level parallelism in different applications to guide the computing resources allocation problem in multicore chips. Up to now, lots of depth researches have been mainly concentrated in the desktop applications. In order to fully understand thread level parallel (TLP) technology's applicability, this paper proposes a criterion for selecting the region to be executed in parallel and analyzes applications' performance impacting factors (computation, coverage parallelism, thread size, inter-thread control dependence feature and inter-thread data dependence feature) by our dynamic profiling tool set. It explores the TLP potentials in desktop, multimedia and High Performance Computing (HPC) fields by demonstrating different speedup potentials that can be exploited using different core numbers. The experimental results show that the majority of desktop applications can only make an effective use of 2 cores' computing resources while most multimedia and HPC applications can use 8-16 cores' computing resources efficiently in the coarse-grain thread-level parallelism. Although TLP technology didn't perform well in the desktop applications that have serious data dependence problem, it's suitable for most multimedia and HPC applications that have large calculation, moderate thread size, and fuzzy dependence but easy to resolve.