A Canonical Multicore Architecture for Network Routers
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
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The stringent requirement for the high efficiency of routing protocol on Internet will be satisfied by exploiting the Threaded Border Gateway Protocol (TBGP) on multi-cores. Since the TBGP performance is restricted by a mass of contentions when racing to access the routing table, a highly-efficient parallel access approach is originally proposed to achieve the ultra-high route processing speed. In this paper, a novel routing table structure consisting of two-level tries is presented for fast parallel access, and a heuristic-based divide-and-recombine algorithm is devised to balance the table accesses and release the contentions, thereby accelerating the parallel route update of multi-threading. By modifying the typical table operations such as lookup, insert, etc., the correctness of two-level tries table is validated according to the operation behaviors of traditional routing table. Experimental results on dual quad-core Xeon server show that the parallel access contentions decrease sharply by 92.5% versus traditional routing table, and the maximal update time per thread is obviously reduced by 56.8% on average with little overhead. Then, the throughput of BGP update message is measured to be improved by about 169%, delivering significant performance improvement of BGP.