Using in-flight chains to build a scalable cache coherence protocol
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 0.00 |
The implementation of multiprocessors cache coherence and memory consistency can help the homemade CPUs support a wide range of system designs. We have made a lot of research on various cache coherence protocols, such as Piranha prototype system, GS320 and AMD64. A directory-based, non-busy, non-blocking Cache Coherence (NB2CC) protocol is introduced here. It divides the serial processing into two steps: conflict detection and conflict solution. Conflict detection is completed at the home node, while conflict solution is distributed to owners. This makes two main contributions: first, unnecessary ordering requirements are eliminated to achieve more concurrency and pipeline performance when conflicts occur; secondly, protocol overhead is much decreased, which brings great applicability to different designs.