EFFEX: an embedded processor for computer vision based feature extraction
Proceedings of the 48th Design Automation Conference
| Hi-index | 0.00 |
This paper describes energy efficient and reconfigurable fused/continuous Multiply-Accumulator (MAC) architecture for single-precision Floating-point and 16-bit signed integer operands. This eight-stage pipelined and single-cycle throughput MAC design contains a bit level pipelined multiplier, followed by fast sparse-tree adder and single cycle accumulator loop with delayed normalization logic. Operation driven energy control is achieved using dynamic clock and fine grained power gating techniques. Power gating is employed in 98% of design to save 79% of leakage power in idle mode, at 1.2V supply and 110C. The use of fully shared logic in the multiplier, accumulator and normalization blocks for different operations enables a compact design of 0.54mm2 containing 117K transistors in eight-metal 65nm CMOS technology. The 15-FO4 design provides 6.8GFLOPS of performance with total energy efficiency of 90mW/GFLOP at 1.2V and 3.4GHz operation.