Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
Ever increasing complexity of SoCs has resulted in starting the system design at a higher level of abstraction. System-level design methodology envisages step-wise refinement of high-level models towards final RTL. However, current practices are limited to only interface-refinement and the true functionality refinement is performed by developing a different model for each abstraction-level. This results in minimal re-use of existing model, loss of efforts and high maintenance cost of multiple models. This paper presents a novel methodology that enables seamless refinement of IP model functionality from one level to another. The presented methodology is generic to be applied to various SoC design tasks. This paper demonstrates the application of the methodology to software energy-estimation for a DSP and functional-cum-timing refinement of DDR-memory model. The proposed methodology resulted in complete re-use of the existing models, easy availability of various model-abstractions and 20% savings in development-effort of a new model.