ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
Trace-driven simulations for a two-level cache design in open bus systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
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In this paper we report on a simulation study that examines a uniprocessor system with a three-level memory hierarchy. A simulation model of a single-cycle-per-instruction processor with a small on-chip cache was constructed and tested with various memory hierarchies. The simulation was intended to focus on meeting the demanding requirements of the latest RISC processors such as the MIPS R4000 and the DEC 21064. The simulator used allowed the authors to run traces of hundreds of millions of memory references per case. These long traces gave a more thorough and accurate picture of the memory demands of current processors. Data is presented enabling a designer to incorporate speed estimates based on implementation restrictions into the process of developing memory hierarchies.