Efficient processing of a rainfall simulation watershed on an FPGA-based architecture with fast access to neighbourhood pixels

  • Authors:

  • Lee Seng Yeong;Christopher Wing Hong Ngau;Li-Minn Ang;Kah Phooi Seng

  • Affiliations:

  • School of Electrical and Electronics Engineering, The University of Nottingham, Selangor, Malaysia;School of Electrical and Electronics Engineering, The University of Nottingham, Selangor, Malaysia;School of Electrical and Electronics Engineering, The University of Nottingham, Selangor, Malaysia;School of Electrical and Electronics Engineering, The University of Nottingham, Selangor, Malaysia

  • Venue:
  • EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
  • Year:
  • 2009

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Abstract

This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow parallel access to the neighbourhood pixel values. In a single read cycle, the architecture is able to obtain all five values of the centre and four neighbours for a 4-connectivity watershed transform. The storage requirement of the multiple bank implementation is the same as a single bank implementation by using a graph-based memory bank addressing scheme. The proposed rainfall watershed architecture consists of two parts. The first part performs the arrowing operation and the second part assigns each pixel to its associated catchment basin. The paper describes the architecture datapath and control logic in detail and concludes with an implementation on a Xilinx Spartan-3 FPGA.