Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Integration, the VLSI Journal
Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A nonbinary LDPC decoder architecture with adaptive message control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a non-binary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.