Concepts and experiments in computational reflection
OOPSLA '87 Conference proceedings on Object-oriented programming systems, languages and applications
Reflective Fault-Tolerant Systems: From Experience to Challenges
IEEE Transactions on Computers
Automatic Insertion of Fault-Tolerant Structures at the RT Level
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Editorial: IP and design reuse
Integration, the VLSI Journal - Special issue: IP and design reuse
Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Dependability Assessment for the Selection of Embedded Cores
EDCC-7 '08 Proceedings of the 2008 Seventh European Dependable Computing Conference
Generic Design and Automatic Deployment of NMR Strategies on HW Cores
PRDC '08 Proceedings of the 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing
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Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilers to automatically deploy such mechanisms on the selected hardware core. Our previous research has already shown the suitability of this approach for the generic design and automatic deployment of NMR strategies. In this paper, we explore the usefulness of the idea in the context of information redundancy. The main contribution is the development of a metaprogram for the provision of ECC-based fault tolerance in data storage elements (registers and memory modules). It is also shown to what extend such metaprogram can be useful for improving the reliability of communications between HW cores in embedded systems.