Implementation of AES encoder using active-HDL

Authors:
J. Dhore;A. P. Thakare
Affiliations:
Sipna's College Of Engg., Amravati, Maharashtra;Sipna's College Of Engg., Amravati, Maharashtra
Venue:
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Year:
2010

Citing 2
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Cryptography and Network Security: Principles and Practice

Cryptography and Network Security: Principles and Practice
High-speed VLSI architectures for the AES algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

With the ever-increasing growth of data communication, the need for security and privacy has become a strong necessity. AES is a symmetric block cipher that is intended to replace DES as the approved standard for wide range of applications. Numbers of hardware techniques have been developed for implementation of AES algorithm. In this paper we are using Active HDL (a third party tool) for the simulation development of AES algorithm encoder based on block RAM feature in FPGA chip. The simulation results are obtained for 128 bit or more than 128 bits of data block with improved throughput and reduced execution time as compared to previous simulation tools.