Fundamentals of Digital Logic with VERILOG Design
Fundamentals of Digital Logic with VERILOG Design
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In a nuclear reactor or process control systems it is required to continuously measure the signals from sensors and transmitters placed at various locations in the field. Accurate measurement of these signal parameters is essential to carry out the control operations effectively. The measured parameters have to be sent to the processor for necessary action. Information about the signals is transmitted to the processor using an Input Output Interface Module (IOIM). This paper describes the design of IOIM using CPLD (Complex Programmable Logic Device). The use of CPLD replaces the TTL IC's present in the system to reduce the board components and improve the system reliability. The reduction in components reduces component density on board, lowers heat dissipation, EMI levels and increases the speed of operation. The reprogramming capability of CPLD enables to change the design instantly for no cost as many times as possible and thereby help in building reconfigurable systems and upgrade system functions as and when required.