Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC's

Authors:
Genemala Haobijam;Roy Paily
Affiliations:
VLSI and Digital System Design Laboratory, Department of Electronics and Communication Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781039;VLSI and Digital System Design Laboratory, Department of Electronics and Communication Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781039
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2010

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Abstract

This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65---95% over conventional planar symmetric inductors and 71---94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC's will be reduced significantly.