System architecture directions for networked sensors
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ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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System architecture for wireless sensor networks
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Communications of the ACM - Wireless sensor networks
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Proceedings of the 2004 international symposium on Low power electronics and design
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An Ultra Low Power System Architecture for Sensor Network Applications
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IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
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Avrora: scalable sensor network simulation with precise timing
IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
GALS SoC interconnect bus for wireless sensor network processor platforms
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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EmNets '05 Proceedings of the 2nd IEEE workshop on Embedded Networked Sensors
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ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
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VLSID '08 Proceedings of the 21st International Conference on VLSI Design
An accelerator-based wireless sensor network processor in 130nm CMOS
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
IEEE Communications Magazine
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this article we describe a low-power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a radio frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS-based WSN applications. The tuning method used minimizes changes to the instruction set architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.