Enhancing the performance of multigrid smoothers in simultaneous multithreading architectures

Authors:
Carlos García;Manuel Prieto;Javier Setoain;Francisco Tirado
Affiliations:
Dto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, Madrid, Spain;Dto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, Madrid, Spain;Dto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, Madrid, Spain;Dto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, Madrid, Spain
Venue:
VECPAR'06 Proceedings of the 7th international conference on High performance computing for computational science
Year:
2006

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Abstract

We have addressed in this paper the implementation of red-black multigrid smoothers on high-end microprocessors. Most of the previous work about this topic has been focused on cache memory issues due to its tremendous impact on performance. In this paper, we have extended these studies taking Simultaneous Multithreading (SMT) into account. With the introduction of SMT, new possibilities arise, which makes a revision of the different alternatives highly advisable. A new strategy is proposed that focuses on inter-thread sharing to tolerate the increasing penalties caused by memory accesses. Performance results on an IBM's Power5 based system reveal that our alternative scheme can compete with and even improve sophisticated schemes based on tailored loop fusion and tiling transformations aimed at improving temporal locality.