Busy-wait barrier synchronization using distributed counters with local sensor

Authors:
Guansong Zhang;Francisco Martínez;Arie Tal;Bob Blainey
Affiliations:
IBM Toronto Lab, Toronto, ON, Canada;IBM Toronto Lab, Toronto, ON, Canada;IBM Toronto Lab, Toronto, ON, Canada;IBM Toronto Lab, Toronto, ON, Canada
Venue:
WOMPAT'03 Proceedings of the OpenMP applications and tools 2003 international conference on OpenMP shared memory parallel programming
Year:
2003

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Abstract

Barrier synchronization is an important and performance critical primitive in many parallel programming models, including the popular OpenMP model. In this paper, we compare the performance of several software implementations of barrier synchronization and introduce a new implementation, distributed counters with local sensor, which considerably reduces overhead on POWER3 and POWER4 SMP systems. Through experiments with the EPCC OpenMP benchmark, we demonstrate a 79% reduction in overhead on a 32-way POWER4 system and an 87% reduction in overhead on a 16-way POWER3 system when comparing with a fetch-and-add implementation. Since these improvements are primarily attributed to reduced L2 and L3 cache misses, we expect the relative performance of our implementation to increase with the number of processors in an SMP and as memory latencies lengthen relative to cache latencies.