SVtL: system verification through logic tool support for verifying sliced hierarchical statecharts

  • Authors:
  • Sara Van Langenhove;Albert Hoogewijs

  • Affiliations:
  • Department of Pure Mathematics and Computer Algebra, Ghent University, Belgium;Department of Pure Mathematics and Computer Algebra, Ghent University, Belgium

  • Venue:
  • WADT'06 Proceedings of the 18th international conference on Recent trends in algebraic development techniques
  • Year:
  • 2006

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Abstract

SVtL is the core of a slicing-based verification environment for UML statechart models.We present an overview of the SVtL software architecture. Special attention is paid to the slicing approach. Slicing reduces the complexity of the verification approach, based on removing pieces of the model that are not of interest during verification. In [18] a slicing algorithm has been proposed for statecharts, but it was not able to handle orthogonal regions efficiently. We optimize this algorithm by removing false dependencies, relying on the broadcasting mechanism between different parts of the statechart model.