Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m)
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Toward a solution of the reverse engineering problem using FPGAs
Euro-Par'06 Proceedings of the CoreGRID 2006, UNICORE Summit 2006, Petascale Computational Biology and Bioinformatics conference on Parallel processing
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We present a method for implementing a fast multiplier for finite fields GF(2m) generated by irreducible trinomials of the form αm + αn + 1. We propose a design based on the Mastrovito multiplier which is described by a parallel/serial architecture that computes a multiplication in m clock cycles by using only bit-adders (XORs), bit-multipliers (ANDs), and shift registers. This approach exploits symmetries and subexpression sharing in Mastrovito matrices in order to reduce the number of operations, and hence computation time in our FPGA implementation. According to preliminary performance results, our approach performs efficiently for large fields and has potential for a variety of applications, such as cryptography, coding theory, and the reverse engineering problem for genetic networks.