ICS '94 Proceedings of the 8th international conference on Supercomputing
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Task selection for a multiscalar processor
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Improving the performance of speculatively parallel applications on the Hydra CMP
ICS '99 Proceedings of the 13th international conference on Supercomputing
Compiler Techniques for the Superthreaded Architectures
International Journal of Parallel Programming
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
ICS '01 Proceedings of the 15th international conference on Supercomputing
Reference idempotency analysis: a framework for optimizing speculative execution
PPoPP '01 Proceedings of the eighth ACM SIGPLAN symposium on Principles and practices of parallel programming
Parallel Programming with Polaris
Computer
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
In Search of Speculative Thread-Level Parallelism
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Min-cut program decomposition for thread-level speculation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
A compiler cost model for speculative parallelization
ACM Transactions on Architecture and Code Optimization (TACO)
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We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectures are small extensions of recently proposed speculative processors. They can extract parallelism speculatively from a sequential instruction stream (implicit threading) and they can execute explicit parallel code sections as a multiprocessor (explicit threading). Although the feasibility of such mixed execution modes is often tacitly assumed in the discussion of speculative execution schemes, little experience exists about their performance and compilation issues. In prior work we have proposed the Multiplex architecture [1], supporting such a scheme. The present paper describes the compilation system of Multiplex. Our compilation system integrates the Polaris preprocessor with the Gnu C code generating compiler. We describe the major components that are involved in generating explicit and implicit threads. We describe in more detail two components that represent significant open issues. The first issue is the integration of the parallelizing preprocessor with the code generator. The second issue is the decision when to generate explicit and when to generate implicit threads. Our compilation process is fully automated.