VLSI-Compatible Immplementations for Artificial Neural Networks
VLSI-Compatible Immplementations for Artificial Neural Networks
Neural Information Processing and VLSI
Neural Information Processing and VLSI
Conic section function neural network circuitry for offline signature recognition
IEEE Transactions on Neural Networks
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In this paper, a neuron and synapse circuitry of Conic Section Neural Network (CSFNN) is presented. The proposed circuit has been designed to compute the Radial Basis Function (RBF) and Multilayer Perceptron (MLP) propagation rules on a single hardware to form a CSFNN neuron. Decision boundaries, hyper plane (for MLP) and hyper sphere (for RBF), are special cases of Conic Section Neural Networks depending on the data distribution of a given applications. Current mode analog hardware has been designed and the simulations of the neuron and synapse circuitry have been realized using Cadence with AMIS 0.5µm CMOS transistor model parameters. Simulation results show that the outputs of the circuits are very accurately matched with ideal curve. Open and closed decision boundaries have also been obtained using designed circuitry to demonstrate functionality of designed CSFNN neuron.