Interblock memory for turbo coding

Authors:
Chia-Jung Yeh;Yeong-Luh Ueng;Mao-Chao Lin;Ming-Che Lu
Affiliations:
Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.;Department of Electrical Engineering, Institute of Communications Engineering, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.;Novatek Microelectronics Corporation, Hsinchu, Taiwan, R.O.C.
Venue:
IEEE Transactions on Communications
Year:
2010

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Abstract

We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding methods are discussed and their performances are evaluated.