Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Eliminating cache conflict misses through XOR-based placement functions
ICS '97 Proceedings of the 11th international conference on Supercomputing
The fractal structure of data reference: applications to the memory hierarchy
The fractal structure of data reference: applications to the memory hierarchy
MemorIES3: a programmable, real-time hardware emulation tool for multiprocessor server design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Full-system timing-first simulation
SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Calculating stack distances efficiently
Proceedings of the 2002 workshop on Memory system performance
Mambo: a full system simulator for the PowerPC architecture
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
Victim management in a cache hierarchy
IBM Journal of Research and Development - Advanced silicon technology
Valgrind: a framework for heavyweight dynamic binary instrumentation
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Parallelization of IBM mambo system simulator in functional modes
ACM SIGOPS Operating Systems Review
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Modeling and evaluating heterogeneous memory architectures by trace-driven simulation
Proceedings of the 2008 workshop on Memory access on future processors: a solved problem?
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
A performance methodology for commercial servers
IBM Journal of Research and Development
Evaluation techniques for storage hierarchies
IBM Systems Journal
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A multi-core memory organization for 3-d DRAM as main memory
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
| Hi-index | 0.00 |
While it is known that lowering the associativity of caches degrades cache performance, little is understood about the degree of this effect or how to lessen the effect, especially in very large caches. Most existing works on cache performance are simulation or emulation based and there is a lack of analytical\ models characterizing performance in terms of different configuration parameters such as line size, cache size, associativity and workload specific parameters. We develop analytical models to study performance of large cache architectures by capturing the dependence of miss ratio on associativity and other configuration parameters. While high associativity may decrease cache misses, for very large caches the corresponding increase in hardware cost and power may be significant. We use our models as well as simulation to study different proposals for reducing misses in low associativity caches, specifically, address space randomization and victim caches. Our analysis provides specific detail on the impact of these proposals, and a clearer understanding of why they do or do not work.