A Computational Approach to Edge Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
Design of FIR Bilevel Laplacian-of-Gaussian filter
Signal Processing
A column parity based fault detection mechanism for FIFO buffers
Integration, the VLSI Journal
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Real time video is used in a wide variety of applications, ranging from video surveillance to medical imaging. These operations require significant amounts of processing power, especially when high resolution frames are used. A large percentage of processing time is used in edge detection kernels. Thus, accelerating these kernels is of vital importance in achieving satisfactory frame rates for real time performance, even in high resolutions. This paper proposes a hardware coprocessor to the Xilinx Microblaze processor which accelerates edge detection significantly, while keeping the hardware requirements low, by using no multipliers at all. Using a Xilinx Spartan 3E FPGA, we have reported a frame rate of 157 frames per second in 4CIF format, which corresponds to a 4x speedup over the software only solution. The speedup was achieved with only 1131 slices and 5 block RAMs hardware occupation, which makes the solution very attractable.