FPGA design methodology for a wavelet-based scalable video decoder

  • Authors:

  • Hendrik Eeckhaut;Harald Devos;Philippe Faes;Mark Christiaens;Dirk Stroobandt

  • Affiliations:

  • Ghent University, ELIS, Parallel Information Systems, Ghent, Belgium;Ghent University, ELIS, Parallel Information Systems, Ghent, Belgium;Ghent University, ELIS, Parallel Information Systems, Ghent, Belgium;Ghent University, ELIS, Parallel Information Systems, Ghent, Belgium;Ghent University, ELIS, Parallel Information Systems, Ghent, Belgium

  • Venue:
  • SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of advantages but the corresponding decoding algorithm is complex and really stresses the system bandwidth as it replaces the blockbased DCT-approach with frame-based wavelets. This has a tremendous impact on the hardware architecture.We present the implementation of the RESUME decoder using reconfigurable hardware designed through the use of state-of-the-art HW/SW-codesign techniques. These techniques were augmented with automatic loop transformations and regression testing. Our efforts resulted in a design capable of decoding more than 25 frames per second at lossless CIF resolution.