A modular coprocessor architecture for embedded real-time image and video signal processing

Authors:
Holger Flatt;Sebastian Hesselbarth;Sebastian Flügel;Peter Pirsch
Affiliations:
Institut für Mikroelektronische Systeme, Gottfried Wilhelm Leibniz Universität Hannover, Hannover, Germany;Institut für Mikroelektronische Systeme, Gottfried Wilhelm Leibniz Universität Hannover, Hannover, Germany;Institut für Mikroelektronische Systeme, Gottfried Wilhelm Leibniz Universität Hannover, Hannover, Germany;Institut für Mikroelektronische Systeme, Gottfried Wilhelm Leibniz Universität Hannover, Hannover, Germany
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

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Abstract

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.