Theoretical Computer Science
Integrating Real Time into Spin: A Prototype Implementation
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
ICALP '92 Proceedings of the 19th International Colloquium on Automata, Languages and Programming
Extending Promela and Spin for Real Time
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Discrete-Time Promela and Spin
FTRTFT '98 Proceedings of the 5th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Verification Diagrams Revisited: Disjunctive Invariants for Easy Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
ICDCS '02 Proceedings of the 22 nd International Conference on Distributed Computing Systems (ICDCS'02)
A Finite State Analysis of Time-Triggered CAN (TTCAN) Protocol Using Spin
ICCTA '07 Proceedings of the International Conference on Computing: Theory and Applications
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
A finite state modeling of AFDX frame management using spin
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
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To overcome the complexity of verification of real-time systems with dense time dynamics, Dutertre and Sorea proposed timeout and calender based transition systems to model real-time systems and verify safety properties using k-induction. In this work, we propose a canonical finitary reduction technique, which reduces the infinite state space of timeout and calender based transition systems to a finite state space. The technique is formalized in terms of clockless finite state timeout and calendar based models represented as predicate transition diagrams. Using the proposed reduction, we can verify these systems using finite state model checkers and thus can avoid the complexity of induction based proof methodology. We present examples of Train-Gate Controller and the TTA startup algorithm to demonstrate how such an approach can be efficiently used for verifying safety, liveness, and timeliness properties using the finite state model checker Spin.