Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
ME64—A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A bandwidth efficient subsampling-based block matching architecture for motion estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Motion estimation is the most important and complex operation in video coding. This paper presents an architecture for motion estimation using Full Search algorithm with 4:1 Pel Subsampling, combined with SAD distortion criterion. This work is part of the investigations to define the future Brazilian system of digital television broadcast. The quality of the algorithm used was compared with Full Search through software implementations. The quality of 4:1 Pel Subsampling results was considered satisfactory, once it presents a SAD result with an impact inferior to 4.5% when compared with Full Search results. The designed hardware considered a search range of [-25, +24], with blocks of 16×16 pixels. The architecture was described in VHDL and mapped to a Xilinx Virtex-II Pro VP70 FPGA. Synthesis results indicate that it is able to run at 123, 4MHz, reaching a processing rate of 35 SDTV frames (720×480 pixels) per second.