The optimum location of delay latches between dynamic pipeline stages

  • Authors:

  • Mahmoud Lotfi Anhar;Mohammad Ali Jabraeil Jamali

  • Affiliations:

  • Islamic Azad University, Khoy, Iran;Islamic Azad University, Shabestar, Iran

  • Venue:
  • APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
  • Year:
  • 2007

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Abstract

Latches are used between pipeline stages to get Minimum Average Latency (MAL). An optimization technique based on introducing a method to search the most proper location of noncompute delay latches between nonlinear pipeline stages is given. The idea is to find a new collision vector which is adaptable with pipeline topology and modifies reservation table, yielding MAL at minimum execution time. This approach not only reduces execution time of hardware, but also minimizes favorite collision vector search time.