An efficient hardware accelerator architecture for implementing fast IMDCT computation

Authors:
Hui Li;Ping Li;Yiwen Wang
Affiliations:
The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, PR China;The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, PR China;The State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, PR China
Venue:
Signal Processing
Year:
2010

Citing 7
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Fast IMDCT and MDCT algorithms - a matrix approach

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Computation of forward and inverse MDCT using Clenshaw's recurrence formula

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Review: A survey of efficient MDCT implementations in MP3 audio coding standard: Retrospective and state-of-the-art

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Abstract

In this paper, a new fast inverse modified discrete cosine transform (IMDCT) algorithm and an efficient hardware accelerator architecture are proposed. The proposed fast algorithm is derived from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) decomposition algorithm. After transformations of DST-IV to DCT-IV and DCT-IV to IDCT-II, the computational items are further recombined to share hardware resources. Experimental results show that the proposed algorithm's computational cycles are decreased by 20% and 51%, respectively compared with two other reported fast algorithms. By employing resource sharing and multiplexing techniques, the proposed hardware accelerator reduces 24% and 48% of transistors compared with two other ones, respectively.